1. Field of the Invention
The present invention relates a data transfer system and method, a data transmitter, a data receiver, a data transmission method, and a data reception method and, more particularly, to a data transfer system and method for multi-bit digital data transfer, a data transmitter, a data receiver, a data transmission method, and a data reception method for the same.
2. Description of the Related Art
Many industrial applications require multi-bit digital data transfer. In many cases, however, multipolar cables and connectors cannot be used because transmission distance or mounting area and volume are limited. Then, various multiplexing approaches are used.
As a typical example of conventional digital data transfer, digital data transfer to a high-definition color liquid crystal monitor of a computer or the like will now be described.
Digital Interface Standards for Monitor as JEIDA standards (http://it.jeita.or.jp/document/publica/standard/summary/Dis m-vlj.pdf) disclose the following techniques for the purpose of multiplexing multi-bit video data, including RGB signals and synchronization signals, for transmission over a transmission line having the small number of electrodes.
According to LVDS (Low Voltage Differential Signaling), seven bits of parallel data is multiplexed by parallel-to-serial conversion to produce a pair of differential signal components. Another pair of differential signal components is used separately from the above pair of signal components in order to transmit a clock signal of the parallel data. A data receiver multiplies the clock signal to generate a clock having a frequency that is seven times as high as that of the clock signal. The generated clock is used to capture serial data. Further, on the basis of the transmitted clock signal, the data receiver obtains timing at which the serial data is converted into parallel data.
According to the principle of LVDS, disadvantageously, even if data multiplexing is improved, at least two transmission lines are inevitably required to transmit data and a clock. Further, if the difference in time between the two transmission lines, namely, skew occurs, the timing of serial-to-parallel conversion in the data transmitter cannot be accurately obtained.
According to TMDS (Transition Minimized Differential Signaling) (trade mark of Silicon Image, Inc.), parallel data is encoded and is then transmitted. Thus, timing of serial-to-parallel conversion can be obtained from the code. Accordingly, the above disadvantage regarding skew is overcome. However, it is necessary to interrupt free data transmission at regular time intervals and transmit a special signal to obtain the timing. Disadvantageously, data cannot be freely transmitted at desired time. Additionally, similar to LVDS, at least two transmission lines are required.
According to GVIF (Giga-bit Video Interface) (trade mark of Sony Corp.), in the minimum configuration, all of image data is combined with a clock into a one-bit signal. Accordingly, a transmission line with the minimum configuration supports one pair of differential signal components. In this case, a separate clock line is not needed. Thus, there is no skew in transmitting data and the clock. Japanese Unexamined Patent Application Publication No. 9-168147 discloses a mechanism of combining a clock and a timing signal for serial-to-parallel conversion with a transmission code according to GVIF.
According to a conventional method disclosed in Japanese Unexamined Patent Application Publication No. 9-168147, a bit clock is extracted from the transition of transmission data and timing of serial-to-parallel conversion is obtained by detecting synchronization (sync) codes (vertical sync data and horizontal sync data). In clock data recovery in which data and a clock are extracted using transition time of transmission data as clock information, frequency misidentification easily occurs. A phenomenon called harmonic lock may occur. Due to harmonic lock, a clock with an abnormal frequency and meaningless data are extracted.
Preventing the above-mentioned harmonic lock requires complex auxiliary means disclosed in Japanese Unexamined Patent Application Publication No. 11-98130.
As mentioned above, in the conventional multi-bit digital data transmission, according to LVDS, at least two transmission lines are needed to transmit data and a clock. Disadvantageously, skew may occur. According to TMDS, it is necessary to interrupt free data transmission at regular time intervals and transmit a special signal in order to obtain timing of serial-to-parallel conversion. Unfortunately, data cannot be freely transmitted at desired time.
GVIF has a disadvantage in that harmonic lock may occur and complex auxiliary means for preventing harmonic lock is needed. According to GVIF, synchronization codes are transmitted infrequently. Unfortunately, if timing of serial-to-parallel conversion in the data transmitter is missed due to noise, it takes time to recover the timing.